RegViz: Visualize HPSICR Bitfield

NXP Semiconductors /MIMXRT1011 /SNVS /HPSICR

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Interpret as HPSICR

LPSVI_EN=LPSVI_EN_0, SV5_EN=SV5_EN_0, SV1_EN=SV1_EN_0, SV0_EN=SV0_EN_0, SV2_EN=SV2_EN_0, SV4_EN=SV4_EN_0, SV3_EN=SV3_EN_0

Description

SNVS_HP Security Interrupt Control Register

Fields

SV0_EN	Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation 0 (SV0_EN_0): Security Violation 0 Interrupt is Disabled 1 (SV0_EN_1): Security Violation 0 Interrupt is Enabled
SV1_EN	Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation 0 (SV1_EN_0): Security Violation 1 Interrupt is Disabled 1 (SV1_EN_1): Security Violation 1 Interrupt is Enabled
SV2_EN	Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation 0 (SV2_EN_0): Security Violation 2 Interrupt is Disabled 1 (SV2_EN_1): Security Violation 2 Interrupt is Enabled
SV3_EN	Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation 0 (SV3_EN_0): Security Violation 3 Interrupt is Disabled 1 (SV3_EN_1): Security Violation 3 Interrupt is Enabled
SV4_EN	Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation 0 (SV4_EN_0): Security Violation 4 Interrupt is Disabled 1 (SV4_EN_1): Security Violation 4 Interrupt is Enabled
SV5_EN	Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation 0 (SV5_EN_0): Security Violation 5 Interrupt is Disabled 1 (SV5_EN_1): Security Violation 5 Interrupt is Enabled
LPSVI_EN	LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section 0 (LPSVI_EN_0): LP Security Violation Interrupt is Disabled 1 (LPSVI_EN_1): LP Security Violation Interrupt is Enabled

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